1. Field of the Invention
The present invention relates to a ferroelectric memory having capacitors composed of ferroelectric films.
2. Description of the Related Art
As the semiconductor memory device having the advantages of all of a DRAM, a flash-memory, and an EEPROM, there has been developed a ferroelectric memory, which has memory cells provided with ferroelectric capacitors. The ferroelectric memory is enabled to hold data even if not fed with a power supply, by operating the ferroelectric capacitors made of an insulating material as a ferroelectric substance, as a variable capacitor and by utilizing the fact that a residual dielectric polarization is left even if the applied voltage to the ferroelectric capacitors is zero. The ferroelectric capacitors can be made of either a ferroelectric material composed mainly of PZT (lead zirconate titanate) or a ferroelectric material having a bismuth layer type perovskite structure such as SBT (strontium bismuth tantalate).
1T1C type cells and 2T2C type cells exist as the memory cells of the ferroelectric memory. The 1T1C type cell is composed of one transfer transistor and one ferroelectric capacitor for holding information of 1 bit. The 1T1C type cell is adopted in the ferroelectric memory for applications of a large capacity, because it can reduce the size of the memory cell. The 2T2C type cell is composed of two transfer transistors and two ferroelectric capacitors for holding information of 1 bit. The 2T2C type cell can enlarge a read margin, because complementary data are stored in the two ferroelectric capacitors. Therefore, the 2T2C type cell is adopted in the ferroelectric memory for applications of a high reliability.
The ferroelectric capacitor of the aforementioned ferroelectric memory has its one end connected with the bit line through a transfer transistor and its other end connected with the plate line. In the read operation of the 2T2C type ferroelectric memory, for example, when the plate line is driven, the voltage difference of the bit line pair changes according to the difference of the effective capacitance of the ferroelectric capacitor pair stored with the complementary data. The voltage difference of the bit line pair is amplified by a sense amplifier and is outputted as read data. The read scheme of this kind is called the “plate line drive scheme”.
The plate line is commonly connected with the numerous ferroelectric capacitors so that the load capacitance is high. In the read operation, therefore, the plate line drive scheme accompanied by a large CR delay has a defect that the read access time becomes long.
In order to shorten the read access time, the inventors of the present application plus others have proposed a scheme (i.e., a differential-capacitance read scheme) for reading the differential-capacitance of the ferroelectric capacitor as data without driving the plate line (Y. Eslami, A. Sheikholeslami, S. Masui, T. Endo, and S. Kawashima, “A differential-Capacitance Read Scheme for FeRAMs”, Digests of Technical Papers of 2002 Symposium on VLSI Circuits, pp. 298-301).
FIG. 1 shows a summary of the differential-capacitance read scheme type read circuit utilizing the 2T2C type ferroelectric memory cells.
A memory cell MC includes transfer transistors M1 and M2 made of nMOS transistors, and ferroelectric capacitors FC1 and FC2. The ferroelectric capacitor FC1 has its one end connected with a bit line BL through the transfer transistor M1 and its other end connected with a plate line PL. The ferroelectric capacitor FC2 has its one end connected with a bit line XBL through the transfer transistor M2 and its other end connected with the plate line PL. The gates of the transfer transistors M1 and M2 are connected with a word line WL. Arrows attached to the ferroelectric capacitors FC1 and FC2, as shown, indicate a polarization state. The upward arrow indicates the state, in which the “logic 0” is stored. The downward arrow indicates the state, in which the “logic 1” is stored.
A sense amplifier SA includes a pair of CMOS inverters having their inputs and outputs connected with each other, and a pair of pMOS transistors P10 and P11. The pMOS transistor P10 has its source, drain and gate connected with a power supply line VDD, the bit line BL and the output CSC (as will also be called the “CSC signal”) of the power supply source, respectively. The pMOS transistor P11 has its source, drain and gate connected with the power supply line VDD, the bit line XBL and the output CSC of the current source, respectively. The pMOS transistors P10 and P11 operate as current sources for feeding electric currents to bit line pairs BL and XBL, respectively.
FIG. 2 shows a hysteresis loop of the ferroelectric capacitor pairs FC1 and FC2 shown in FIG. 1.
When the plate line is driven from a low level to a high level so that a voltage V1 is applied between the two ends of the ferroelectric capacitor, the ferroelectric capacitor FC1 stored with the “logic 0” is not accompanied by a polarization inversion so that the effective capacitance C0 becomes small. On the contrary, the ferroelectric capacitor FC2 stored with the “logic 1” is accompanied by the polarization inversion so that the effective capacitance C1 becomes large. By the drive of the plate line PL, voltages corresponding to electric charges Q0 and Q1 are generated on the bit lines BL and XBL.
FIG. 3 shows the read operation of the 2T2C type ferroelectric capacitor shown in FIG. 1.
In the read operation, the bit lines BL and XBL are first precharged to a ground voltage VSS. When a read command is fed so that the word line WL is selected in response to an address signal, the ferroelectric capacitors FC1 and FC2 are connected with the bit lines BL and XBL, respectively.
After this, the output CSC of the current source, which is pulled up to the power supply voltage VDD, is set to a DC voltage value (at a low level). In response to the change of the CSC signal to the low level, the bit lines BL and XBL are fed with electric currents of the same quantity through the pMOS transistors P10 and P11. At this time, the rising rates of the bit lines BL and XBL are different according to the effective capacitances of the ferroelectric capacitors FC1 and FC2. Specifically, the bit line BL, which is connected with the ferroelectric capacitor FC1 having an effectively smaller capacitance, rises earlier than the bit line XBL which is connected with the ferroelectric capacitor FC2 having an effectively larger capacitance.
The voltages of the bit lines BL and XBL continue rising while the CSC signal is at the low level. After a sufficient voltage difference was built up between the bit lines BL and XBL, the CSC signal changes again to the power supply voltage VDD so that the current source composed of the pMOS transistors P10 and P11 is turned OFF. After this, power supplies SAP and SAN of sense amplifiers SAP and SAN change to the high level and the low level, respectively, thereby to activate the sense amplifier SA. In response to this activation of the sense amplifier SA, the voltage of the bit line BL rises to the voltage (e.g., the power supply voltage VDD) of the power supply SAP of the sense amplifier, and the voltage of the bit line XBL falls to the voltage (e.g., the ground voltage VSS) of the power supply SAN of the sense amplifier. During the activation of the sense amplifier SA, the plate line PL is driven so that the original data are written back in the ferroelectric capacitors FC1 and FC2. After this, the word line WL is unselected, and the read operation is completed.
In the differential-capacitance read scheme, as shown in FIG. 3, the plate line PL is driven after the data were read from the ferroelectric capacitors FC1 and FC2. Independently of the CR delay time of the plate line, therefore, the data can be read from the memory cell MC to the bit lines BL and XBL. Therefore, it is possible to shorten the data reading time (i.e., the time from the read command to the output of the read data). Specifically, the data reading time is made shorter by about 40% than that of the plate line drive scheme.
FIG. 4 shows a summary of a read circuit of a differential-capacitance read scheme utilizing the 1T1C type ferroelectric memory cell. The sense amplifier SA is identical to the sense amplifier SA shown in FIG. 1.
Each memory cell MC includes the transfer transistor M1 made of an nMOS transistor, and the ferroelectric capacitor FC1. This ferroelectric capacitor FC1 has its one end connected with a bit line BLE or a bit line BLO through the transfer transistor M1 and its other end connected with the plate line PL. The gates of the transfer transistors M1 of the memory cells MC are individually connected with different word lines WLE and WLO. In other words, the memory cells MC, which are individually connected with the complementary bit lines BLE and BLO, are not simultaneously accessed to.
A reference memory cell RMC includes: a reference capacitor composed of the same four ferroelectric capacitors C0 and C1 as the ferroelectric capacitor FC1 of the memory cell MC; and two nMOS transistors N10 and N11. When a reference word line RWLO is at the high level, the nMOS transistor N10 connects the reference capacitor with the bit line BLE. When a reference word line RWLE is at the high level, the nMOS transistor N11 connects the reference capacitor with the bit line BLO.
The reference capacitor is constituted by connecting the two capacitor pairs, in which the ferroelectric capacitor C0 for storing the “logic 0” and the ferroelectric capacitor C1 for storing the “logic 1” are connected in series, in parallel with each other. The capacitance of the reference capacitor is (C0+C1)/2. In other words, the reference capacitor has an intermediate capacitance between the capacitance of the ferroelectric capacitor FC1 for storing the “logic 0” and the capacitance of the ferroelectric capacitor FC1 for storing the “logic 1”. The reference capacitor is configured by combining the same plural ferroelectric capacitors as the memory cell capacitors, so that the intermediate capacitance can be made simple and highly precise.
In the 1T1C type ferroelectric memory shown in FIG. 4, in case the word line WLE takes the high level so that the memory cell MC connected with the bit line BLE is selected, the reference word line RWLE takes the high level so as to connect the reference capacitor with the bit line BLO. Likewise, in case the word line WLO takes the high level so that the memory cell MC connected with the bit line BLO is selected, the reference word line RWLO takes the high level so as to connect the reference capacitor with the bit line BLE. Like FIG. 3, as has been described hereinbefore, the difference between the voltage of the bit line BLE (or BLO) changing according to the capacitance of the ferroelectric capacitor FC1 and the voltage of the bit line BLO (or BLE) changing according to the capacitance of the reference capacitor is amplified by the sense amplifier SA and is outputted as the read data.
The differential-capacitance read scheme can shorten the read access time more than the plate line drive scheme. However, it is demanded to make the read access time shorter.
In the 1T1C type differential-capacitance read scheme, the reference memory cell is configured by using a plurality of ferroelectric capacitors. In the ferroelectric capacitors, the relation between the applied voltage and the capacitance is nonlinear, as shown by the hysteresis loop of FIG. 2. Specifically, the ferroelectric capacitor FC1 stored with the “logic 0” as shown in FIG. 2, and the ferroelectric capacitor FC1 stored with the “logic 1” are different in the change in the capacitance with respect to the change in the applied voltage. In fact, the effective capacitance of the reference memory becomes smaller than (C0+C1)/2. As a result, the read margin of the memory cell MC stored with the “logic 0” becomes smaller than the read margin of the memory cell MC stored with the “logic 1”.
The reference memory cell can also be constituted of one ferroelectric capacitor having a larger size than that of the ferroelectric capacitor FC1 of the memory cell. The effective capacitance of the reference memory cell of this kind can be set between the capacitances C0 and C1, as shown in FIG. 2, by writing the “logic 0” in the ferroelectric capacitor. However, the effective capacitance of the reference memory cell is hard to set precisely to (C0+C1)/2. Therefore, the read margin becomes small.
In the ferroelectric memory, on the other hand, the ferroelectric material is deteriorated when the read number (or the rewrite number) exceeds tenth power of 10, so that the shape of the hysteresis loop shown in FIG. 2 changes to reduce a residual dielectric polarization value Q. When the ferroelectric memory is mounted on a printed circuit board, the residual dielectric polarization value Q is temporarily reduced by the influences of thermal fluctuations caused by a soldering process (or a heat treatment). The residual dielectric polarization value Q is allowed to restore the value before the soldering process by a first read operation after the heat treatment.
In the ferroelectric memory (FIG. 4) sharing the reference memory cell between the memory cells MC connected with the plural word lines WLE and WLO, the change in the residual dielectric polarization value Q before and after the heat treatment reduces the read margin. In the first read operation after the heat treatment, the residual dielectric polarization value Q has reduced in both the memory cells MC and in the reference memory cell so that its reductions are offset by each other. Therefore, the read margin hardly drops. In case, however, an access is made in the next read operation to another memory cell MC which has not restored the residual dielectric polarization value Q, the reference memory cell has restored the residual dielectric polarization value Q. Therefore, the read margin has dropped, and the data may be unable to be correctly read.
In the ferroelectric memory (FIG. 4) sharing the reference memory cell between the memory cells MC connected with the plural word lines WLE and WLO, the access time of the reference memory cell is twice at the maximum as many as that of the memory cells MC. Therefore, the material characteristics of the ferroelectric capacitor constituting the reference memory cell are earlier deteriorated than those of the ferroelectric capacitor of the memory cells MC. As a result, the read margin becomes smaller as the read number becomes larger, so that the read number (or the rewrite number) decreases.
In order to prevent the reduction in the read margin in the 1T1C type ferroelectric memory, there has been proposed a technique (Japanese Unexamined Patent Application No. 2002-157876), in which the average of the maximum and the minimum obtained by the read operation of the ferroelectric capacitor is set to the reference voltage. According to this technique, the number of the memory cells MC to be connected with the word lines WL is increased by one, in which the inverted data of the data to be written in the memory cell MC connected with a predetermined bit line are written. In this ferroelectric memory, however, the operation of the sense amplifier cannot be started until the reference voltage is generated from the ferroelectric capacitor. As a result, the access time is delayed.